In the case of nonvolatile memories (EEPROM, flash, EPROM, OTP, . . . ), one terminal of the memory cell is always at a fixed potential, for example ground potential. This line is the so-called source line. The other terminal of the memory cell is connected to the so-called bit line. The memory cell is read via the bit line.
If the bit line is not active, that is to say if a read-out operation is not being effected, then the bit line, to which a precharge potential is applied from the previous read-out operation, can be discharged via a conductive memory cell since the memory cell is connected by its other terminal to the source line carrying ground potential.
If the bit line is selected, then its parasitic capacitances have to be charged with the precharge potential by the sense amplifier connected to the bit line. This results in a correspondingly long read access time of the memory cell.
A description has been given of performing the so-called charging of the parasitic capacitances of the bit line prior to the read-out thereof by the sense amplifier in the sequence of the read access by means of a specific arrangement, as disclosed in DE 100 53 956 A1.
In this case, what has proved to be disadvantageous is that the operation of precharging the bit line has to be started at a specific point in time prior to the read-out. This means that it is necessary to generate an additional external signal for precharging of the bit line, it being necessary to effect corresponding processing of this signal and synchronization with the read-out operation. The read access is thus divided into two phases, the phase of precharging the bit line disadvantageously taking up a specific time. Fast sense amplifiers are regulating devices which reach their operating point relatively slowly in the case of a large change in potential, thereby resulting in specific time losses.
U.S. Pat. No. 5,812,456 describes an integrated, nonvolatile memory in which the bit line selection is not performed in the customary manner by means of a drain-side selection transistor that charges the selected bit line to a specific precharge voltage. Instead, provision is made of a source-side switching transistor that enables, in the selected state, a current flow via the bit line that is fixedly connected to the evaluation device.